I have been interested in the limits of RISC (Reduced Instruction Set Computer) architecture for a while and recently came across OISC (One Instruction Set Computer) \ URISC (Ultimate RISC) architecture when looking for a simple way to implement a Virtual Machine for an A.I. project I was working on. It has to be one of the easiest architectures to implement in either software or hardware and this is the main reason for its design as a teaching aid. It has only one instruction, hence the name, which isn’t the best name considering that most processors have one instruction set. URISC is good, but perhaps OIC (One Instruction Computer) would have been more accurate.
There are a number of types of OISCs, but this article will concentrate on those using the SUBLEQ instruction, as this is the one that I favour. Mention should also be made of those using the SUBNEG instruction which is very similar. Because there is only one instruction, only the operands are specified, which in this case consists of 3 memory addresses that are acted on as explained below: ### SUBLEQ (Subtract and Branch if Less then or Equal to zero)
SUBLEQ a, b, c Mem[b] := Mem[b] - Mem[a] if (Mem[b] ≤ 0) goto c
SUBNEG (Subtract and Branch if Negative)
SUBNEG a, b, c Mem[b] := Mem[b] - Mem[a] if (Mem[b] < 0) goto c
There are a number of implementation options for a SUBLEQ processor:
- Negative numbers could refer to Input/Output ports.
- Relative addressing could be used rather than direct addressing.
- If an address is used as an Input/Output port, then this could copy the data rather than run SUBLEQ on it.
- The branch destination could refer to a memory location that contains the actual branch destination, i.e.
goto mem[c]instead of
Programming Using Macros
To program the SUBLEQ OISC machine we can create a set of Macros to ease development. Below are some simple examples of useful macros that could be implemented. The contents of each Macro consists of previously defined macros or 3 memory location references to be executed by the SUBLEQ instruction. Where the third operand is missing, it is assumed to be the location of the next instruction, i.e. it doesn’t conditionally branch. Mem[Z] is assumed by most of the macros to contain zero.
It can been seen that by building up macros and using certain memory locations in a standard way, that it is relatively easy to program this type of machine.
There are, of course, many more memory accesses per operation than most standard processors which will make object code larger and will have a negative speed impact. The speed of the processor could be increased, however, by running some instructions in parallel. This could be done by running several instructions at the same time if they are using different operands and aren’t branching.
There isn’t much about SUBLEQ OISC computers on the internet. However I have found the following to be useful: * A SUBNEG computer built using 7400 series logic chips * Oleg Mazonka’s page discussing a self interpreter for a SUBLEQ virtual machine. It also includes an assembler and interpreter. * The Wikipedia article on One Instruction Set Computers
I have also written a follow up article: Hello, World! in SUBLEQ Assembly.
I hope that you find this interesting and would love to hear of any uses that you find for it.