Improving the Standard SUBLEQ OISC (One Instruction Set Computer) Architecture
Written by Lawrence Woodman on 15th May 2009
Tags: Computer Architecture, OISC, SUBLEQ
When I first came across The SUBLEQ URISC (Ultimate RISC) / OISC (One Instruction Set Computer) Architecture, I really liked the beauty and simplicity of the design.  However, I have now been experimenting with it for quite a while and have noticed one aspect of the standard implementation that I am not so happy with.  In the standard implementation, negative numbers are used for Input/Output Ports or to Halt the machine in the case of a branch destination.  This seems such as waste of the negative numbers, as generally only a couple will be used meaning that nearly half of the addressing capacity is lost for little gain.  I propose the following improvement to the standard SUBLEQ design.

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Hello‚ World! in SUBLEQ Assembly
Written by Lawrence Woodman on 29th March 2009
Tags: OISC, Programming, SUBLEQ
After writing a previous article: The SUBLEQ URISC (Ultimate RISC) / OISC (One Instruction Set Computer) Architecture.  I was left thinking that I should really have given at least a "hello, world" program as a demonstration.  I was then inspired after seeing John Metcalf's post: Hello World for the RSSB Virtual Computer.  This showed that these OISCs don't require as much code as people may think to do what you want.  So here is my version of a "hello, world" program for the SUBLEQ Architecture. 

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The SUBLEQ URISC (Ultimate RISC) / OISC (One Instruction Set Computer) Architecture
Written by Lawrence Woodman on 5th March 2009
Tags: Computer Architecture, OISC, SUBLEQ
I have been interested in the limits of RISC (Reduced Instruction Set Computer) architecture for a while and recently came across OISC (One Instruction Set Computer) \ URISC (Ultimate RISC) architecture when looking for a simple way to implement a Virtual Machine for an A.I. project I was working on.  It has to be one of the easiest architectures to implement in either software or hardware and this is the main reason for its design as a teaching aid.  It has only one instruction, hence the name, which isn't the best name considering that most processors have one instruction set.  URISC is good, but perhaps OIC (One Instruction Computer) would have been more accurate.

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